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Model and Design of Improved Current Mode Logic Gates by Kirti Gupta & Neeta Pandey & Maneesha Gupta

Model and Design of Improved Current Mode Logic Gates by Kirti Gupta & Neeta Pandey & Maneesha Gupta

Author:Kirti Gupta & Neeta Pandey & Maneesha Gupta
Language: eng
Format: epub
ISBN: 9789811509827
Publisher: Springer Singapore


4.3.1.2 Design of a Dy-DCML-NN Inverter

In the evaluation phase, the logic function is evaluated due to the formation of a conduction path between CL and C1 depending on the inputs. The transfer of charge from the CL to C1 takes place resulting in a decrease in the output node potential. The charge transfer continues till both the capacitors attain equal potential. Thus, it is necessary to ensure that charge transfer ceases only when the potential of the output node is reduced by VSWING. This can be accomplished by proper sizing of capacitor C1. By using charge conservation principle, we can write



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