Microprocessors and MicroControllers: For Learners by Gloobal Techno


Microprocessors and MicroControllers: For Learners by Gloobal Techno

Author:Gloobal Techno [Techno, Gloobal]
Language: eng
Format: azw3
Published: 2018-09-27T16:00:00+00:00



Keyboard Entry in FIFO Ram

The status of the shift key and control key are also stored with the keycode as shown in figure.

When a key is pressed, the corresponding 8-bit keycode is loaded into the first location of the FIFO RAM. Then the interrupt request line (IRQ) is made high to indicate that the FIFO RAM is not empty.

(ii)Display Section:

The display section consists of 16 × 8 display RAM and display register hold the address of the word currently being written or read by the CPU and the two 4-bit nibbles being displayed.

The 8279 can drive a maximum of 16 display digits.

The 16 × 8(16 numbers of 8-bit buffer RAM) display RAM hold the 8-bit data for 16 display digits. The 16-display digits are multiplexed.

The display section of 8279 has eight output lines divided into two groups OUT A6 - OUT A3 and OUT B0 – OUT B3.

These lines provide the 8-bit segment information for the display digits.

The line is used to blank the display.

(iii)Scan Section:

The scan section consist of a scan counter and four scan lines (SL0 – SL4).These scan counter can be operated in two modes namely Encoded mode and Decoded mode.

In the encoded mode, the counter provides a binary count which can be decoded to provide the scan lines for the key board or display. (That is the 4 scan lines periodically output 0 to 15).

In the decoded mode the scan counter itself is a decoder. That is the least significant two bits are decoded and decoded output are available in the scan lines (SZ3 – SL0).

The four scan lines (SL3 - SL0) are common to keyboard and display. These lines are used to form the digit driver of a multiplexed display and rows of a matrix keyboard.

iv)CPU Interface Section:

The CPU interface section consist of Data Buffer, Input/Output control and control and timing registers.

The data buffer has 8-bi-directional data lines DB7 – DB0 to transfer data between 8279 and the microprocessor.

The CPU interface section also has other control lines and A0 to interface the 8279 with the system bus.

The 8279 has an interrupt request line (IRQ) to indicate that a valid key data is available in FIFO RAM.

The 8279 requires an internal clock signal (100 KHz) to refresh the display and to scan the keyboard. There are two register namely command register and Data register. The control line is used to select one of these two register.



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